San Jose, CA; Tokyo, Japan; Shanghai, China; June 1, 2011: GRID Simulation Technology, Inc. (GRID), the leader in SPICE-accurate EMIR verification and sign-off solutions for low-power electronic designs, and ProPlus Design Solutions, Inc. (ProPlus), the device modeling technology leader, announced a strategic partnership to deliver the most accurate and fastest EMIR signoff solution for very large-low power designs. The integration of ProPlus modeling technology with GRID’s hierarchical power network analysis delivers for the first time, a full-chip, device level simulation of EMIR effects in low-power designs.
Low power design and verification teams face growing sign-off challenges at advanced process nodes. Power network analysis tools, which are critical to tape-out and successful silicon, typically utilize reduction techniques to speed up runtime performance at the expense of accuracy and tool-to-tool traceability. GRID’s hierarchical analysis eliminates the need for reduction methods and delivers complete visibility of the power behavior of all nodes in a design.
"We provide designers a scalable SPICE-accurate qualification and verification solution for EMIR simulation,” said Wai Yan Ho, CEO of GRID. “For the first time in the industry, customers receive a detailed hierarchical report providing 100% visibility and traceability of nodal values, branch currents, independent loops, and total power consumption for device, IP block, and complex SoCs with GRID and Proplus tools and methodology. I look forward to our future cooperation with ProPlus.”
"As technology scales down, low power designs require more accurate and scalable verification solutions. While many of the solutions today have to trade off the accuracy for performance, the joint efforts of ProPlus and GRID have made a breakthrough in EMIR simulation," said Dr. Zhihong Liu, Executive Chairman of ProPlus. “We are happy to work with GRID in delivering this much needed industry solution.”
GRID is an Electronic Design Automation (EDA) company delivering the world's largest and most complex low-power electronic design, verification and sign-off solutions at true SPICE-accuracy through its revolutionary new verification and sign-off technology. The company's core technology NanoRAIL, and HPDA (hierarchical, parallel, distributed, architecture) platform provides multiple products for SPICE-accurate analysis of IC power grid problems including IR voltage drop and electro-migration (EM), and the qualification of complex power network analysis results. GRID’s products include: NanoRAIL-HGP, NanoRAIL-SoC, NanoRAIL-TR, NanoSource, SimCHECK, and GRIDViewer. GRID is a privately held California Corporation headquartered in Morgan Hill, CA with offices in: East Fishkill, NY; and Tokyo, Japan.
NanoRAIL-HGP, NanoRAIL-SoC, NanoRAIL-TR, NanoSource, SimCHECK, and GRIDViewer are trademarks of GRID Simulation Technology, Inc.
For more information about GRID see: www.gridsimtech.com
BSIMProPlus, NanoDesigner and NanoVerifier are trademarks of ProPlus Design Solutions, Inc.
Leading Experts in EDA and Simulation Join Forces with Company to Guide Low-Power Technology Strategy
San Jose, CA and Tokyo Japan; May 17th 2011 – GRID Simulation Technology, the leader in SPICE-accurate EMIR verification and sign-off solutions for low-power electronic designs, announced the formation of its Technical Advisory Board (TAB) and the appointment of the Board's founding members. These members are; Mutsuo Saito, Sr Fellow and VP of Engineering at Toshiba Semiconductor and Ward Veracruysse, former Fellow and Director of EDA at AMD.
GRID’s TAB members provide strategic guidance to address current and future low-power design challenges through GRID’s patented and patent-pending methods utilizing multi-core platforms and soon to be announced technologies.
“I am honored to be working with GRID and their new and exciting offerings” said Mitsuo Saito. “I hope GRID’s simulation capability can offer significant improvements in RCL simulation providing stationary numeric results that are necessary to verify EMIR quality of results and total power consumption of designs. Today’s low power SoCs designers face challenging electrical design requirements. GRID’s computational functions can fill a critical need for verification and sign-off of functionality, timing, and reliability. I look forward to working in close collaboration with GRID and their Technical Advisory Board members.
“Recent product failures at advanced process nodes highlight the increasing need for SPICE-accurate EMIR simulation and verification methods” said Ward Vercruysse. Fast-SPICE simulators that rely on model order reduction and higher level abstractions result in information loss and loss of traceability when one verifies how the circuit is supposed to work. Tools that employ these techniques are fundamentally flawed as verification and sign-off tools. GRID’s unique approach avoids these steps and provides a much needed solution. I am excited to be working with GRID as a member of their Technical Advisory Board.
"We are forming this Technical Advisory Board to accelerate the adoption of SPICE-accurate EMIR simulation analysis, verification, and sign-off for low-power designs." said Wai Yan Ho, President and CEO of GRID. "We are honored by the acceptance of our founding members, who are recognized and distinguished leaders in EDA with extensive knowledge in simulation tools and multi-core processing methods. GRID customers can look forward to reaping the benefits of their collaboration through innovative, new product offerings and technologies from GRID that will drastically increase the industry’s EMIR simulation, analysis, and sign-off capabilities for giga-scale designs to address today’s and tomorrow’s most challenging low power design requirements."
Mitsuo Saito received the BSEE and MSEE degrees from the Electronic Engineering division of the University of Tokyo in 1972 and 1974, respectively. He then joined Toshiba Corporation's Research and Development Center. From 1984 to 1985, he was assigned as a visiting scholar to the MIT Media Lab, where he did research into 3-D graphics and human computer interface.
From 1986, Mr. Saito started a 3-D graphics chip development project, which later led to the chip adopted for the Sony Playstation 1. Then, from 1997, he became Director of Toshiba’s System ULSI Engineering Lab where he was responsible for the development of the graphics processor chip for Sony's Playstation 2.
In July 2001, he became Chief Fellow of Toshiba’s in-house semiconductor Company and took charge of the Broadband System LSI project, which has developed the Cell Processor and its peripheral chips. As of 2007, Mr. Saito became Vice President of Engineering, Toshiba Semiconductor Company
Ward Vercruysse is a design automation expert. He started his career in Silvar-Lisco, one of the first publicly traded EDA (electronic design automation) companies. He developed analog (electrical) and digital (dsp) simulator. At Silicon Compiler Systems, another innovative EDA pioneer, he worked on circuit analysis and optimization, and design frameworks.
At Sun Microsystems (now Oracle) he took on various roles. He created and managed the CAD group responsible for internally developed analysis tools tuned for high performance design and he architected various electrical verification and optimization tools. As a senior manager he was responsible for the complete design environment for the UltraSparc family. As a Distinguished Engineer, his focus was on improving the processes and the tool integrations to improve productivity.
At Advanced Micro Systems, Ward was a Fellow and Director of CAD, responsible for the design environment used to design the 64bit single and multi core micro processors. His main interests are Technology, CAD (algorithm, framework, data models, analysis, optimization) and Processes (and lack thereof) in engineering organizations. Ward has a MSEE (Magna Cum Laude), from the University of Leuven, Belgium and an MBA, from Santa Clara University, Santa Clara, California.
NanoRAIL-HGP, NanoRAIL-SoC, NanoRAIL-TR, NanoSource, SimCHECK, and GRIDViewer are trademarks of GRID Simulation Technology, Inc.
GRID Simulation Technology, Inc. (GST), a Silicon Valley-based Electronic Design Automation (EDA) company announced today it has joined the ARM® Connected Community® eco-system of partners, the industry's largest ecosystem of ARM technology-based products and services. As part of the ARM Connected Community, GST gains access to the full range of ARM resources to market and deploy innovative solutions to IC design teams looking for a faster way to get their ARM Powered® products to market.
"We are excited to be working with ARM, their customers, and foundry partners to deliver a much needed solution to address power integrity challenges in ARM based designs implemented in advanced processes," said John L. Kulusich, VP Business Development at GST. "At 65nm and below, the need for SPICE-accurate electromigration and IR drop (EMIR) verification and sign-off has moved to center stage. NanoRAIL-TR and SimCHECK provides today's ARM customers a breakthrough in capacity, accuracy and speed of analysis. The ARM ecosystem can now use a new hierarchical methodology for analysis of power/ground/substrate networks and critical signal and clock nets in complex, giga-scale, low power designs."
The ARM Connected Community is a global network of companies aligned to provide a complete solution, from design to manufacture and end use, for products based on the ARM architecture. ARM offers a variety of resources to Community members, including promotional programs and peer-networking opportunities that enable a variety of ARM Partners to come together to provide end-to-end customer solutions. Visitors to the ARM Connected Community have the ability to contact members directly through the website.
“The Connected Community is all about companies working together to provide the most complete solutions in the shortest possible time. By joining the Community, which now comprises more than 725 companies, GRID Simulation Technology increases the large portfolio of skills, products and services that are centered around the ARM architecture, and currently available to developers worldwide,” said Lori Kate Smith, partnership marketing manager for ARM.
For more information about the ARM Connected Community, please visit: http://www.arm.com/communityGRID Simulation Technology, Inc. is a Silicon Valley-based Electronic Design Automation (EDA) company dedicated to solving the world's largest and most complex electronics problems at true SPICE-accuracy through its revolutionary new analysis technology. The company's flagship products, NanoRAIL-TR and SimCHECK, provide analysis of IC power grid problems including IR voltage drop and electro-migration (EM), and the qualification of complex power, ground, signal and clock network analysis results. The company is a privately held California Corporation headquartered in Morgan Hill, CA with offices located in: Irvine, CA; East Fishkill, NY; and Tokyo, Japan.
For more information about NanoRAIL-TR and SimCHECK, please contact: This e-mail address is being protected from spambots. You need JavaScript enabled to view it
GRID Simulation Technology, Inc.
1295 East Dunne Avenue, Suite 215
Morgan Hill, CA 95037
NanoRAIL-TR™, SimCHECK™, and HPDA™ are registered trademarks of GRID Simulation Technology, Inc. ARM and ARM Connected Community are registered trademarks of ARM Limited. Cortex, and MPCore are trademarks of ARM Limited. All other brands or product names are the property of their respective holders. “ARM" is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiaries ARM Inc.; ARM KK; ARM Korea Limited.; ARM Taiwan Limited; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Germany GmbH; ARM Embedded Technologies Pvt. Ltd.; ARM Norway, AS and ARM Sweden AB.
GRID Simulation Technology, Inc. (GST), a Silicon Valley-based Electronic Design Automation (EDA) company announced NanoRAIL-TR, the industry’s first hierarchical, parallel, distributed architecture (HPDA™) Electromigration and IR drop (EMIR) simulator for SPICE-accurate, giga-scale, transistor-level analysis, and sign-off of mixed-signal, memory, analog and I/O circuit designs. NanoRAIL-TR’s unique HPDA architecture takes advantage of both standalone and networked multi-core systems delivering breakthrough speed, accuracy, and capacity. HPDA scales linearly on standalone and networked multi-core systems.
Today’s low power IC designs implemented in advanced processes, require SPICE-accurate EMIR analysis to simulate, model, and verify large complex power delivery networks to ensure low power circuit performance, manufacturability, and product reliability. To handle these complex power networks, EMIR simulators employ hidden reduction methods to simplify the size of the networks being analyzed. While these methods reduce runtimes, they may cause a critical loss of accuracy in simulation and the loss of traceability between simulation results and the original circuit under evaluation.
NanoRAIL-TR’s Loss-less Partitioning™ technology delivers SPICE accuracy and does not use reduction methods in network, model, or matrix calculations. It strictly adheres to Kirchhoff’s Voltage Law (KVL), Kirchhoff’s Current Law (KCL), and the Power conservation law for all nodes without exception, providing fundamentally consistent EMIR simulation results. 100% node reporting, and 1-to-1 traceability between EMIR analysis and the physical design netlist are unique features of NanoRAIL-TR. To ensure easy integration into design flows, NanoRAIL-TR works with industry proven layout extractors and SPICE simulators.
"High capacity, SPICE accurate analysis, modeling, and reporting functions are required for efficient EMIR simulation, verification, and sign-off,” said Mitsuo Saito, Chief Fellow and VP of Engineering, Toshiba Semiconductor. "Standard integration with trusted layout extraction and SPICE simulation tools using proven data formats reduces risks and improves benefits. This approach provides access to NanoRAIL-TR’s EMIR analysis, modeling and reporting capabilities without having to re-qualify proven extractor and circuit simulator functions. We look forward to continuing success working with GRID Simulation Technology in Toshiba Semiconductor’s advanced process low power design methodologies.
“We are excited to be working Toshiba Semiconductor with NanoRAIL-TR and SimCHECK to addresses their critical low-power needs for advanced process designs,” said Wai Yan Ho, CEO of GST. “NanoRAIL-TR provides SPICE-accurate results. GST’s HPDA simulation methodology delivers to Toshiba design teams a hierarchical modeling architecture that improves EMIR analysis quality of results (QoR), quickly calculates total power consumption, and improves design performance and reliability. We will continue to introduce new innovative technologies to meet the challenges facing IC designers.”
GRID Simulation Technology, Inc. is a Silicon Valley-based Electronic Design Automation (EDA) company dedicated to solving the world's largest and most complex electronics problems at true SPICE-accuracy through its revolutionary new analysis technology. The company's flagship products, NanoRAIL and SimCHECK, provide analysis of IC power grid problems including IR voltage drop and electro-migration (EM), and the qualification of complex power network analysis results. The company is a privately held California Corporation headquartered in Morgan Hill, CA with offices located in: Irvine, CA; East Fishkill, NY; and Tokyo, Japan.
Contact: John L Kulusich This e-mail address is being protected from spambots. You need JavaScript enabled to view it
GRID Simulation Technology, Inc.
1295 East Dunne Avenue, Suite 215
Morgan Hill, CA 95037
NanoRAIL™ TR, SimCHECK™, HPDA™. and Loss-less Partitioning™ are trademarks of GRID Simulation Technology, Inc.
GRID Simulation Technology, Inc. (GST), a Silicon Valley-based Electronic Design Automation (EDA) company delivering SPICE accurate simulation and verification solutions to solve the world's most complex electronics problems, today announced it has joined Virage Logic Corporation‟s VIP Partner Program to promote SPICE-accurate power integrity sign-off for semiconductor memory IP. GST provides giga-scale SPICE-accurate solutions for analysis of IC power grid problems including IR voltage drop and electro-migration (EM) and the qualification of complex power network analysis results. The Virage Logic VIP Partner Program brings together technology and business alliances with Design Services, EDA and Test, Foundry, and Intellectual Property (IP) partner companies to provide a broad range of complementary solutions for System-on-Chip (SoC) design.
Current generation EMIR analysis tools suffer from limitations in speed, capacity, and accuracy when analyzing IP blocks and complex SoCs. To handle these „oversized‟ problems, these EMIR simulators often employ hidden reduction methods to reduce the size of the networks being analyzed. While these methods are effective in reducing runtimes, they immediately cause accuracy loss in simulation and as well as the loss of traceability between simulation results and the original circuit under evaluation. Unfortunately, there has been no “Golden Numeric” reference to identify and quantify where these tradeoffs are made. To ensure the manufacturability of designs, a consistent Quality of Result (QoR) from EMIR simulation is necessary to verify any trade-offs made; and to understand any introduced source(s) of error. With SimCHECK, circuit design, CAD, and verification teams now have a “no compromises” EMIR Verification capability to qualify the results of any simulation result independent of EDA tool, computational method, and technology modeling technique.
"The VIP Partner Program‟s mission is to help increase interoperability and provide access to complete solutions that enable mutual customers to accelerate silicon success by reducing design time and improving manufacturability,” said Joel Rosenberg, Senior Marketing Director for Virage Logic. “As the semiconductor industry's trusted IP partner, we look forward to working with GRID Simulation Technology to address customer power integrity sign-off for designs using our ASAP™, STAR™ and advanced SiWare™ Memory IP.”
"SimCHECK provides complete numeric verification of EMIR analysis results with 100% reporting and traceability of nodal values to verify quality QoR, total power consumption, and the manufacturability of IP blocks and SoC designs,” said John L. Kulusich, Vice President, Business Development, GST. “Joining Virage Logic‟s VIP Partner Program is the next step in GST‟s plan in delivering solutions to answer customer needs for power integrity verification and sign-off and improved manufacturability analysis. We look forward to accelerated customer and silicon success working as part of Virage Logic‟s VIP Partner Program.”
GRID Simulation Technology, Inc. is a Silicon Valley based Electronic Design Automation (EDA) company dedicated to solving the world's largest and most complex electronics problems at true SPICE-accuracy through its revolutionary new analysis technology. The company's flagship products, NanoRAIL™ and SimCHECK™, provide analysis of IC power grid problems including IR voltage drop and electro-migration (EM), and the qualification of complex power network analysis results. The company is a privately held California Corporation headquartered in Morgan Hill, CA with offices located in: Irvine, CA; East Fishkill, NY; and Tokyo, Japan.
This e-mail address is being protected from spambots. You need JavaScript enabled to view it
GRID Simulation Technology, Inc.
1295 East Dunne Avenue, Suite 215
Morgan Hill, CA 95037
NanoRAIL™, and SimCHECK™ are trademarks of GRID Simulation Technology, Inc.
ASAP™, STAR™, and SiWare™ Memory are trademarks of Virage Logic Corporation.
GRID Simulation Technology, Inc. (GST), a Silicon Valley design automation startup, today announced it has joined Si2 as a result of the company's increased presence in the electro-migration (EM) and power integrity (IR drop) simulation and verification market. GST will be making available to Si2 its hierarchical design format for circuit analysis.
"Electrical design-for manufacturability (eDFM) modifies a design to physically optimize and measurably affect electrical performance " said Jake Buurma, Vice-President of Si2. "GST has experience with large, hierarchical netlist formats and their expertise is a welcome addition to Si2. They will help us better address a comprehensive design flow that addresses eDFM interoperability challenges.”
GST will participate in the Design for Manufacturability Coalition Workshop - "A New Era for DFM" on Sunday, June 13, 2010 at the Design Automation Conference, Anaheim, Calif. The event takes place in room 207C, 1:00pm to 4:00pm, Anaheim Convention Center.
“We’re enthused to be part of the Si2 DFM Workshop and I look forward to working with Si2 as well as Si2’s member companies.” said Bob Pack, Chief Technologist eDFM, GST. “At GST we are focused on providing solutions to the world’s largest and most complex electronic simulation challenges. We see a real trend where giga-scale problems require nano-scale detail without any accuracy compromises.”
"Engineers need a standard approach to address the exploding complexity for sign-off of conventional and new 3D integrated circuit designs” said John L. Kulusich, vice president, Business Development, GRID Simulation Technology Inc. “Joining Si2 is the next step in GRID’s plan to address customer needs for EM and IR drop sign-off accuracy and interoperability. We look forward to working in collaboration with Si2 and Si2 member companies.”
GRID Simulation Technology, Inc. is a Silicon Valley based Electronic Design Automation (EDA) company dedicated to solving the world's largest and most complex electronics problems at true SPICE-accuracy through its revolutionary new analysis technology.
The company's flagship products, NanoRAIL™ and SimCHECK™, provide analysis of IC power grid problems including IR voltage drop and electro-migration (EM), and the qualification of complex power network analysis results.
The company is a privately held California Corporation headquartered in Morgan Hill, CA with offices located in: Los Angeles, CA; East Fishkill, NY; and Tokyo, Japan.
This e-mail address is being protected from spambots. You need JavaScript enabled to view it
GRID Simulation Technology, Inc.
1295 East Dunne Avenue, Suite 215
Morgan Hill, CA 95037
NanoRAIL™, and SimCHECK™ are trademarks of GRID Simulation Technology, Inc.
GRID Simulation Technology today announced SimCHECK, a qualification tool for verifying the accuracy of the Electromigration and IR drop (EMIR) simulation results of complex networks such as power grids, signal and clock nets, and silicon substrates in IP Blocks, and SoCs.
Today’s generation of low power SoCs manufactured at advanced process nodes are challenged by competing and often conflicting electrical design requirements; high computational functions, low power operating budgets, and increasingly higher frequencies. ICs designed to meet these requirements are susceptible to transient noise effects due to the high density of the transistors and miles of interconnect wiring. Unseen variations in IR voltage drop can have dramatic impacts on product yields in terms of leakage, performance, and reliability. Qualified, SPICE accurate, EMIR analysis is now a critical mandate for verification and sign-off of functionality, timing, and reliability of these designs.
Current generation EMIR analysis tools suffer from limitations in speed, capacity, and accuracy when analyzing large IP blocks and complex SoCs. To handle these ‘oversized’ problems, EMIR simulators often employ reduction methods to simplify the size of the networks being analyzed. While these methods are effective in reducing runtimes, they immediately create unknown sources of loss of accuracy in simulation, and the loss of traceability between simulation results and the original circuit under evaluation. Unfortunately, there has been no “Golden Numeric” reference to identify and quantify where tradeoffs are made. To ensure manufacturability of designs, a consistent Quality of Result (QoR) from EMIR simulation is necessary to verify if any trade-offs made are acceptable; and to understand any introduced sources of error.
SimCHECK provides today’s designer a rigorous method to designers to numerically account for all EMIR impacts on their designs and verify the results from any EMIR simulator utilizing Kirchhoff’s Voltage Law (KVL), Kirchhoff’s Current Law (KCL), and Power Conservation Law.
SimCHECK automatically identifies and maps non-compliant values to the exact XY location on the physical netlist and easily integrates with popular EDA tools utilizing standard industry formats.
“SimCHECK is very helpful to ensure the quality of result of IP design blocks and the entire IC design,” said Mitsuo Saito, Senior Fellow and VP of Engineering, Toshiba Semiconductor. “Numeric verification of IR voltage drop and electro-migration analysis is a necessary step to verify Quality of Results, total power consumption, and the manufacturability of designs when using multiple simulation tools.”
“SimCHECK reads, qualifies, traces, and report all simulation accuracy errors for any complex network,” said Wai-Yan Ho, CEO of GRID Simulation Technology. “Finally, CAD teams and designers now have a network analysis with no compromises to qualify the results of any simulator and reduction method. With SimCHECK as a new golden reference tool, we expect design teams will use the benefits of better analysis to create higher performance designs with greater reliability and fewer failures.”
GRID Simulation Technology, Inc. is a Silicon Valley-based Electronic Design Automation (EDA) company dedicated to solving the world's largest and most complex electronics problems at true SPICE-accuracy through its revolutionary new analysis technology.
The company's flagship products, NanoRAIL and SimCHECK, provide analysis of IC power grid problems including IR voltage drop and electro-migration (EM), and the qualification of complex power network analysis results.
The company is a privately held California Corporation headquartered in Morgan Hill, CA with offices located in: Los Angeles, CA; East Fishkill, NY; and Tokyo, Japan..
This e-mail address is being protected from spambots. You need JavaScript enabled to view it
GRID Simulation Technology, Inc.
1295 East Dunne Avenue, Suite 215
Morgan Hill, CA 95037
NanoRAIL™ and SimCHECK™ are trademarks of GRID Simulation Technology, Inc.
