GRID’s TAB members provide strategic guidance to address current and future low-power design challenges through GRID’s patented and patent-pending methods utilizing multi-core platforms and soon to be announced technologies.
“I am honored to be working with GRID and their new and exciting offerings” said Mitsuo Saito. “I hope GRID’s simulation capability can offer significant improvements in RCL simulation providing stationary numeric results that are necessary to verify EMIR quality of results and total power consumption of designs. Today’s low power SoCs designers face challenging electrical design requirements. GRID’s computational functions can fill a critical need for verification and sign-off of functionality, timing, and reliability. I look forward to working in close collaboration with GRID and their Technical Advisory Board members.
“Recent product failures at advanced process nodes highlight the increasing need for SPICE-accurate EMIR simulation and verification methods” said Ward Vercruysse. Fast-SPICE simulators that rely on model order reduction and higher level abstractions result in information loss and loss of traceability when one verifies how the circuit is supposed to work. Tools that employ these techniques are fundamentally flawed as verification and sign-off tools. GRID’s unique approach avoids these steps and provides a much needed solution. I am excited to be working with GRID as a member of their Technical Advisory Board.
"We are forming this Technical Advisory Board to accelerate the adoption of SPICE-accurate EMIR simulation analysis, verification, and sign-off for low-power designs." said Wai Yan Ho, President and CEO of GRID. "We are honored by the acceptance of our founding members, who are recognized and distinguished leaders in EDA with extensive knowledge in simulation tools and multi-core processing methods. GRID customers can look forward to reaping the benefits of their collaboration through innovative, new product offerings and technologies from GRID that will drastically increase the industry’s EMIR simulation, analysis, and sign-off capabilities for giga-scale designs to address today’s and tomorrow’s most challenging low power design requirements."
Mitsuo Saito received the BSEE and MSEE degrees from the Electronic Engineering division of the University of Tokyo in 1972 and 1974, respectively. He then joined Toshiba Corporation's Research and Development Center. From 1984 to 1985, he was assigned as a visiting scholar to the MIT Media Lab, where he did research into 3-D graphics and human computer interface.
From 1986, Mr. Saito started a 3-D graphics chip development project, which later led to the chip adopted for the Sony Playstation 1. Then, from 1997, he became Director of Toshiba’s System ULSI Engineering Lab where he was responsible for the development of the graphics processor chip for Sony's Playstation 2.
In July 2001, he became Chief Fellow of Toshiba’s in-house semiconductor Company and took charge of the Broadband System LSI project, which has developed the Cell Processor and its peripheral chips. As of 2007, Mr. Saito became Vice President of Engineering, Toshiba Semiconductor Company
Ward Vercruysse is a design automation expert. He started his career in Silvar-Lisco, one of the first publicly traded EDA (electronic design automation) companies. He developed analog (electrical) and digital (dsp) simulator. At Silicon Compiler Systems, another innovative EDA pioneer, he worked on circuit analysis and optimization, and design frameworks.
At Sun Microsystems (now Oracle) he took on various roles. He created and managed the CAD group responsible for internally developed analysis tools tuned for high performance design and he architected various electrical verification and optimization tools. As a senior manager he was responsible for the complete design environment for the UltraSparc family. As a Distinguished Engineer, his focus was on improving the processes and the tool integrations to improve productivity.
At Advanced Micro Systems, Ward was a Fellow and Director of CAD, responsible for the design environment used to design the 64bit single and multi core micro processors. His main interests are Technology, CAD (algorithm, framework, data models, analysis, optimization) and Processes (and lack thereof) in engineering organizations. Ward has a MSEE (Magna Cum Laude), from the University of Leuven, Belgium and an MBA, from Santa Clara University, Santa Clara, California.
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